10x eTalks : Virtual Memory Session with Simon Southwell
Continuing with our tradition of #10xETalks, 10xEngineers was honored to host Simon Southwell (a retired logic, software and systems designer with 30+ years of experience in Electronics Research and Development) to speak about Virtual Memory and Memory Management Unit in one of our recent sessions. Simon talked about how the introduction of virtual memory has revolutionized memory management in modern processors. Before Virtual Memory, OS could run only one process at a time, A process running would have access to all address space without having to contend with other processes. The demand for more sophisticated and efficient #memorymanagement system increased over time as the applications and processes became more memory intensive and the requirement of them being run in parallel increased. Virtual Memory based memory subsystems allow multiple processes to run in parallel where each process has an illusion of having the accessibility of all address space. Virtual memory is supported by the mutual operation of the OS and a dedicated logic in hardware known as MMU (Memory Management unit). Virtual memory uses the concept of address translation where each process has its own set of translation tables. Generally, the address translations are kept in TLB (Translation lookaside buffer) which acts as a cache of the address translations. A miss in the TLB would result in fetching the translations from the RAM by doing the page table walk which can be done either in hardware with the dedicated logic referred to as Page Table Walker or by the OS which would be a much slower process. He discussed about the page faults and the page swapping where RAM being the cache of pages, if missed, causes a Page Fault. In the case of Page Faults, OS is responsible for fetching the pages from the Disk storage and storing it in the RAM. He also briefly explained different translation schemes in RISC-V i.e. SV32, SV39, and SV48 as well. The session advanced with a discussion on types of caches i.e. VIVT(Virtually indexed and Virtually Tagged), PIPT(Physically indexed and Physically Tagged), and VIPT(Virtually indexed and Physically Tagged) with VIPT being the most commonly used technology. The session concluded with a healthy Q/A session at the end. Thank you very much, Simon Southwell!