The goal of these talks is two-fold; to foster learning and to pay it forward. Happening once every week, these talks provide a platform where everyone can come together to learn from and teach each other as well as provoke conversations that matter. These talks cover a wide range of topics and are not only limited to the technical domain.
One such talk featured Roger Espasa, CEO & Founder at Semidynamics Technology Services. The talk focused on the challenges of designing an out-of-order #riscv Vector Unit and how Roger and his team accomplished this feat. Some of the topics which #Roger talked about included the basic working of #vector instructions, the importance of renaming in Out-of-Order Core Implementation, Mask register management, and Instructions crossing an LMUL boundary. #Semidynamics currently has two (Avispado: https://lnkd.in/dESvNjBQ & Atrevido: https://lnkd.in/dxYPh7dN) RISC-V IP cores available for licensing, an in-order and an out-of-order 64-bit vector core.
Thank you very much, Roger!