Enhancing RISC-V Core Performance with New Extensions
RISC-V has emerged as a promising and open-source alternative in the ever-evolving landscape of processor architectures. As the demand for computational power continues to surge, enhancing the performance of RISC-V cores becomes imperative.
Engineers at 10xEngineers are exploring different ways in which the capabilities of RISC-V cores can be enhanced. Their focal point has been OpenHW Group’s CVA6 core which is an open-source application-class RISC-V processor. Recently 10xEngineers added the RISC-V Bit-Manipulation ISA-extensions to the CVA6 core. Bit manipulation instructions result in better system performance due to improved code density, improved runtime efficiency, and low power consumption. The RISC-V base Instruction Set Architecture (ISA) doesn’t support bit manipulation instructions. However, due to RISC-V architecture’s modularized instruction extension support a set of bit manipulation extensions (Zba, Zbb, Zbc, Zbs) were recently ratified. The team at 10xEngineers has implemented the bit manipulation extensions on the CVA6 processor.
A quantitative analysis on size and power improvement has been performed with the help of FPGA and ASIC synthesis data and has been published in ACM.
The data shows that a standard CVA6 implemented on a FPGA versus a CVA6 with the Bitmanip extensions results in a 4% reduction in dynamic power for RV64 (5% improvement for RV32), 12.5% improvement in code size for RV64 Linux image (9% improvement for RV32) at a cost of 4% increase in LUTs for an FPGA implementation (3% increase in gate count for ASIC implementation.) We have also seen an 18% speed-up and 4% code size reduction in the results of the Dhrystone benchmark.