RISC-V Architecture Compatibility Testing (ACT) and RISCOF, Allen Baum’s Talk
10xEngineers has been engaged with university students and faculty members in the past, to bridge the gap between industry and academia. This time 10x Engineers hosted a three-day RISC-V Hackathon for students and professionals to come and get hands-on working experience with open-source RISC-V Infrastructure, and tools, and ultimately be able to contribute to the community. Students from #UET, #lums , #namal, and #itu participated in the Hackathon.
Muhammad Tahir, chairperson of the Electrical Engineering department, and Ubaid Ullah Fayyaz , an associate professor in the Electrical Engineering department at UET Lahore were invited as guests at the opening ceremony where they talked about their experiences and the future of #riscv . The event started with a welcome note from the CEO, Bilal Zafar. As the event progressed, participants learned about RISC-V Architecture Compatibility Testing (ACT) and its open-source framework (RISCOF) and tried to port this framework with different RISC-V cores. On the second day of the event, Allen Baum, chair of RISC-V International’s sig-arch group, joined us for a talk where he talked about how he has witnessed the evolution of microprocessor technology since its beginning, and how RISC-V will revolutionize the semiconductor marketplace. On the last day of the Hackathon, we had our keynote speaker, S Pawan Kumar, RTL design engineer at InCore semiconductors. Pawan gave a comprehensive talk on RISC-V Compatibility Testing, its framework, and the prospects of ACTs.
At the end of the event, participants were successfully able to port notable open-source RISC-V cores which include SWERV EH1, SWERV EL2, PICORV32, IBEX, and other in-house developed cores to the ACT framework.