During the 2024-25 academic year, 10xEngineers has sponsored a Global Clinic Project to develop open-source architectural functional coverage for RISC-V microprocessors. The project has involved students and faculty at Harvey Mudd College in California and UET and Habib University in Pakistan. 10xEngineers liaisons have mentored the students and trailblazed several of the critical technical components. The project has produced open-source testplans, SystemVerilog coverpoints, and tests for both RV32 and RV64 through the RVA22S64 profile, for unprivileged instructions as well as privileged features including CSRs, exceptions, interrupts, virtual memory, and endianness https://github.com/openhwgroup/cvw-arch-verif. The 10xEngineers liaisons specifically have contributed the testplans and coverpoints for virtual memory, which is the most complex portion of the functional coverage, as well as guiding students through extending riscv-arch-test to hit these coverpoints. They have also integrated the riscvISACOV framework to collect coverage from a device under tests via the RISC-V Verification Interface (RVVI), guided students writing subtle SystemVerilog coverpoints, and met weekly to advise the student teams. We expect the students will be able to finish the remaining SV48, PMP, and interrupt coverpoints in the next month. This work will bring the OpenHW Foundation CORE-V Wally processor https://github.com/openhwgroup/cvw to Technology Readiness Level 5 and will greatly ease getting other RVA22S64 and simpler cores to a similar level of verification. It is also being considered by the RISC-V Certification Steering Committee as a basis for open-source certification. The team has submitted a paper to the 2025 RISC-V summit describing their work. Overall, it has been a delight collaborating with 10xEngineers. Their deep technical knowledge, hard work, and long-standing commitment to the RISC-V open-source ecosystem have made this project possible.