Job Description:
We are seeking an engineer with strong technical expertise in Python, FPGA, AI, and Medical Imaging. The ideal candidate will have hands-on experience with Verilog/SystemVerilog for RTL design and a solid grasp of digital design fundamentals, including finite state machines and pipeline architectures. Expertise in synchronous design, clock domain crossing, and low-power design techniques is essential, as is a knack for debugging and solving complex design challenges. Exposure to RISC-V architecture, processor design, and experience with EDA tools such as Synopsys, Cadence, or Mentor Graphics is a plus. This role is perfect for candidates holding a Bachelor’s or Master’s degree in Electrical or Computer Engineering (or a related field) with 0–3 years of experience.
Key Responsibilities:
- Key responsibilities
- Assist in the design and development of digital circuits, including RTL coding using Verilog/SystemVerilog.
- Work with senior engineers to implement microarchitecture specifications for various IPs.
- Perform functional and performance analysis of digital blocks and subsystems.
- Support timing analysis, synthesis, and verification of digital designs.
- Collaborate with verification teams to ensure coverage closure and bug fixes.
- Participate in design reviews and provide documentation for implemented designs.
- Team structure
- You will work in a cross-functional team of digital designers and verification engineers.
- Growth potential (career path, future responsibilities)
- Opportunity to grow into a Senior Design Engineer role, taking ownership of IP blocks.
- Exposure to RISC-V processors, custom accelerators, and cutting-edge semiconductor designs.
- Potential to lead design projects as you gain experience.
Required Skills & Qualifications
- Must-have technical skills (e.g., Python, FPGA, AI, Medical Imaging)
- Verilog/SystemVerilog for RTL design.
- Digital design fundamentals, including finite state machines and pipeline architectures.
- Knowledge of synchronous design, clock domain crossing (CDC), and low-power design techniques.
- Strong problem-solving skills and ability to debug design issues.
- Preferred skills (nice-to-have but not essential)
- Exposure to RISC-V architecture and processor design.
- Experience with EDA tools (e.g., Synopsys, Cadence, Mentor Graphics).
- Understanding of ASIC/FPGA design flows, including synthesis, timing analysis, and place-and-route.
- Basic scripting knowledge (Python, Perl, Tcl) for automation.
- Education level & certifications (if needed)
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Years of experience
- E1 (0–3 years of experience)
Unique Aspects of the Role
- Unique aspects of the role (e.g., cutting-edge technology, leadership opportunities)
- Work on cutting-edge semiconductor IPs with a highly skilled team.
- Hands-on exposure to RISC-V processor development and advanced digital design methodologies.
- Access to industry-leading EDA tools and methodologies
- How is 10xEngineers better?
- Collaborate with top RISC-V companies and open-source projects.
- Opportunity to work on both open-source and commercial-grade semiconductor designs.
- Fast-paced growth opportunities and potential to lead projects.
Additional skills
We are looking for an engineer who took responsibility for communicating and attending open-source community meetings. This role requires strong listening, speaking, and note-taking skills.