Staff Engineer – Design & Verification
Location: Barcelona, Spain
Employment Type: Full-Time
Experience Level: Senior / Staff
Role Overview
We are seeking a highly skilled Staff Engineer to lead the design and verification of advanced digital IPs and subsystems. This role focuses on architecturally complex environments involving out-of-order execution cores, memory hierarchy, cache coherency protocols, and high-speed interconnects such as PCIe and UCIe. The ideal candidate will collaborate with system architects to define micro-architectures, drive RTL development, and lead verification strategies from planning to closure.
Key Responsibilities
- Lead micro-architecture definition and refinement for out-of-order cores, load/store units, memory subsystems, and interconnect logic.
- Develop synthesizable RTL using SystemVerilog with a focus on modularity, scalability, and timing closure.
- Architect and implement comprehensive verification environments using UVM, including testbench components, sequences, monitors, and scoreboards.
- Own the verification plan encompassing coverage-driven verification, assertion-based checks, and formal verification techniques.
- Integrate and verify protocols including Coherent Hub Interface (CHI), AMBA (AXI, AHB, APB), PCIe, and UCIe.
- Validate cache coherency protocols such as MESI/MOESI and memory ordering across multi-core systems.
- Perform deep debug and root-cause analysis using industry-standard tools (e.g., Verdi, DVE, SimVision).
- Drive verification closure through functional and code coverage, regression stability, and automation.
- Collaborate with physical design, firmware, and validation teams for seamless integration.
- Mentor junior engineers and promote a culture of technical excellence.
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- 7+ years of experience in digital design and verification, including leadership roles.
- Expertise in SystemVerilog, UVM, and simulation/debug environments (VCS, Questa, Verdi).
- Hands-on experience with CHI, AMBA (AXI, AHB, APB), PCIe, and UCIe protocols.
- Strong understanding of out-of-order execution, instruction pipelines, branch prediction, and hazard resolution.
- Solid knowledge of memory hierarchy, including L1/L2/L3 caches, TLBs, MMUs, and cache coherency protocols.
- Proficiency in scripting languages and tools such as Makefiles, Python, Perl, Tcl, and C.
- Familiarity with formal verification, assertion-based verification, and functional coverage metrics.
- Excellent communication and cross-functional collaboration skills.
Preferred Skills
- Experience with RISC-V, ARM, or custom instruction set architectures.
- Exposure to FPGA prototyping, emulation platforms, and post-silicon validation.
- Knowledge of DFT, scan insertion, and testability strategies.
- Contributions to open-source hardware or verification frameworks.
- Familiarity with version control systems (Git, Perforce) and CI/CD workflows.
What We Offer
- Dynamic, innovation-driven environment with cutting-edge projects.
- Opportunities to lead architecture and verification strategies across multiple domains.
- Competitive compensation, performance incentives, and comprehensive benefits.
- Access to industry conferences, training programs, and technical mentorship.
- A culture that values precision, ownership, and continuous improvement.