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  • High-quality scaling, built for real-time pipelines

Polyphase Video Scaler IP for premium upscaling & downscaling

A high-performance FPGA soft-IP core delivering sharp visuals with low latency, true arbitrary scaling factors, and native anti-aliasing — designed for display controllers, imaging pipelines, and embedded systems.
Explore features
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Throughput

Up to 4K @ 60fps

Real-time streaming
Scaling

Arbitrary factors

H & V independent
Quality

Multi-tap polyphase

Anti-aliasing built-in

Optimized for AMD® Xilinx® Ultrascale+™. FPGA-agnostic RTL structure supports porting to other devices.

At a glance

Fast read for integration + quality knobs
  • Ultrascale+ optimized
  • FPGA-agnostic RTL

  • Separable H/V

Horizontal + vertical stages in series to reduce resource cost while maintaining quality.

  • AXI interfaces

AXI4-Stream I/O + AXI4-Lite control for clean SoC + FPGA integration.
Input range

240×240 → 4K

Taps

4 / 6 / 8 / 10 / 12

Phases

64

FEATURES

Built for real products, not demos

A highly optimized, synthesizable soft core — engineered for predictable throughput, high quality, and practical integration.

  • Flexible scaling

From 240×240 to 4K, arbitrary horizontal/vertical factors (not limited to integer ratios).

  • FPGA agnostic design

Optimized for AMD® Xilinx® Ultrascale+™ (portable RTL structure for other FPGAs).

  • Polyphase filter engine

Multi-tap, multi-phase FIR interpolation delivering superior quality and anti-aliasing.

  • Adjustable taps & phases

Taps: 4 / 6 / 8 / 10 / 12, Phases: 64.

  • Latency & throughput

Low latency pipeline, supports full real-time throughput for many formats up to 4K@30fps.

  • Bypass / pass-through

1:1 pass mode when scaling isn’t required — keep system behavior deterministic.

WHY POLYPHASE

Scaling is easy to do — hard to do well

Basic interpolators (nearest, bilinear) can resize frames, but they often trade away frequency response: edges blur, fine patterns alias, and downscales shimmer. Polyphase multi-tap filtering is built to preserve detail while controlling aliasing, across both upscales and downscales.

 

  • Nearest / simple blends

  • Fast, but visible jaggies / blockiness
  • Aliasing on fine textures
  • Not great for professional output

  • Bilinear (2×2)

  • Smoother than nearest
  • Soft edges, lost micro-contrast
  • Downscaling needs extra anti-aliasing

  • Polyphase multi-tap

  • Better frequency response
  • Sharper detail, reduced aliasing
  • Native anti-aliasing for downscales

HOW IT WORKS

Separable H/V polyphase filtering

Two stages — horizontal then vertical — each implemented as a multi-tap, multi-phase FIR. Coefficients are selected per phase (fractional position), enabling high-quality interpolation for arbitrary ratios.

  • Multi-tap FIR

Configurable taps (4–12) to balance quality vs resources.

  • 64 phases

Phase banks represent sub-pixel positions for consistent detail.

  • Anti-aliasing built-in

Downscales remain stable without extra AA blocks.

  • Low latency pipeline

Streaming architecture for real-time paths.

Pipeline view

Conceptual block flow

AXI4-Stream Input

RGB / YCbCr, 8/10/12-bit (cfg dependent)

Horizontal & Vertical Polyphase FIR

multi-tap filtering + Line buffering + phase-aligned interpolation

AXI4-Stream Output

Low-latency scaled stream

Bypass mode

1:1 pass-through when scaling is not needed.

Coefficient banks

Static or dynamic loading via AXI4-Lite.
Note: exact buffering depends on format, taps, and throughput configuration.

FORMAT & INTEGRATION

Video-friendly I/O and control

Designed for streaming pipelines while exposing the knobs you actually need: scaling parameters and coefficient banks.
  • Video format support
Config dependent
  • RGB 4:4:4
  • YCbCr 4:2:0
  • YCbCr / YC 4:2:2
  • 8 / 10 / 12 bpc
  • Interfaces
  • AXI4-Stream for input/output video streaming
  • AXI4-Lite for programming and runtime control
  • Programmable coefficients

Support for dynamically or statically loaded coefficient banks — select responses for different product modes.

Configuration knobs

Typical product controls
Scaling factors

Arbitrary H / V ratios

Independent per axis
Filter complexity

4–12 taps

Quality ↔ resources
Phase resolution

64 phases

Sub-pixel alignment
Memory strategy

BRAM / URAM options

Pixel-rate dependent
For higher pixel rates, the scaler can be optimized to utilize URAMs instead of BRAMs (configuration dependent).

Technology-independent soft IP Core for FPGA, ASIC and SoC devices (license: EULA).

APPLICATIONS

Where polyphase scaling pays off

If your product needs stable detail, controlled aliasing, and predictable latency, polyphase filtering becomes a quiet enabler — especially in premium video and imaging.

  • Broadcast imaging

Real-time 4K scaling with low latency and high fidelity across formats — built for professional pipelines.

  • Video conferencing

Clean resizes across mixed sources (camera + content) with consistent sharpness and fewer artifacts.

  • Media walls

Ultra-smooth 4K scaling, precise alignment, and dependable visuals for multi-display systems.

  • VR headsets

Low latency and crisp imagery — critical when scaling content into display-native panels.

  • Medical imaging

High-fidelity 4K scaling that preserves fine diagnostic detail, supports low-latency visualization, and enables high-quality interpolation in medical display pipelines.

RESOURCE UTILIZATION

Measured with OOC flow (Vivado)

Utilization results are captured using Vivado out-of-context (OOC) flow. Surrounding design impacts placement and routing, so treat these as guidance. At higher pixel rates, memory can be optimized toward URAM instead of BRAM (configuration dependent).

 
Ask for utilization table
Request demo build

Example configuration matrix

Replace with your measured data
FPGAScaler ConfigurationResource Utilization
Max WidthMax HeightInput FormatOutput FormatPixel Bit WidthTapsPixels per clockLUTFFBRAMsURAMsDSP
1zu5ev384021604204208613528244213044
2zu5ev3840216042042081217552411622080
3zu5ev384021604204201012110052552436080
5zu5ev3840216042042012615290338421.5044
6zu5ev384021604204201212111348688636.5080
7zu5ev40962160444444864141419425018198
8zu5ev4096216044444410641518210452018198
9zu5ev4096216044444412642220613902018198
Final numbers depend on format, taps, pixel rate, memory strategy, and surrounding pipeline.

NEXT STEP

Want to see it in your pipeline?

Share your formats, resolutions, and target device. We’ll map a configuration (taps/phases/memory strategy) and provide integration package details.

  • Integration-ready interfaces
    AXI4-Stream + AXI4-Lite
  • Low-latency streaming
    Built for real-time systems
  • Quality knobs that matter
    Taps, phases, coefficients
  • Portability
    Structured RTL for porting

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Polyphase Video Scaler IP
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