- High-quality scaling, built for real-time pipelines
Polyphase Video Scaler IP for premium upscaling & downscaling
Up to 4K @ 60fps
Arbitrary factors
Multi-tap polyphase
Optimized for AMD® Xilinx® Ultrascale+™. FPGA-agnostic RTL structure supports porting to other devices.
At a glance
- Ultrascale+ optimized
- FPGA-agnostic RTL
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Separable H/V
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AXI interfaces
240×240 → 4K
Taps
4 / 6 / 8 / 10 / 12
64
FEATURES
Built for real products, not demos
A highly optimized, synthesizable soft core — engineered for predictable throughput, high quality, and practical integration.
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Flexible scaling
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FPGA agnostic design
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Polyphase filter engine
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Adjustable taps & phases
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Latency & throughput
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Bypass / pass-through
WHY POLYPHASE
Scaling is easy to do — hard to do well
Basic interpolators (nearest, bilinear) can resize frames, but they often trade away frequency response: edges blur, fine patterns alias, and downscales shimmer. Polyphase multi-tap filtering is built to preserve detail while controlling aliasing, across both upscales and downscales.
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Nearest / simple blends
- Fast, but visible jaggies / blockiness
- Aliasing on fine textures
- Not great for professional output
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Bilinear (2×2)
- Smoother than nearest
- Soft edges, lost micro-contrast
- Downscaling needs extra anti-aliasing
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Polyphase multi-tap
- Better frequency response
- Sharper detail, reduced aliasing
- Native anti-aliasing for downscales
HOW IT WORKS
Separable H/V polyphase filtering
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Multi-tap FIR
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64 phases
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Anti-aliasing built-in
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Low latency pipeline
Pipeline view
AXI4-Stream Input
Horizontal Polyphase FIR
Vertical Polyphase FIR
AXI4-Stream Output
Bypass mode
Coefficient banks
FORMAT & INTEGRATION
Video-friendly I/O and control
- Video format support
- RGB 4:4:4
- YCbCr 4:2:0
- YCbCr / YC 4:2:2
- 8 / 10 / 12 bpc
- Interfaces
- AXI4-Stream for input/output video streaming
- AXI4-Lite for programming and runtime control
- Programmable coefficients
Support for dynamically or statically loaded coefficient banks — select responses for different product modes.
Configuration knobs
Arbitrary H / V ratios
4–12 taps
64 phases
BRAM / URAM options
Technology-independent soft IP Core for FPGA, ASIC and SoC devices (license: EULA).
APPLICATIONS
Where polyphase scaling pays off
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Broadcast imaging
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Video conferencing
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Media walls
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VR headsets
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Medical imaging
RESOURCE UTILIZATION
Measured with OOC flow (Vivado)
Utilization results are captured using Vivado out-of-context (OOC) flow. Surrounding design impacts placement and routing, so treat these as guidance. At higher pixel rates, memory can be optimized toward URAM instead of BRAM (configuration dependent).
Example configuration matrix
| Config | Resolution / Rate | Taps | Phases | BRAM | URAM | DSP | LUT | FF |
|---|---|---|---|---|---|---|---|---|
| A | 1080p @ 60 | 8 | 64 | — | — | — | — | — |
| B | 4K @ 30 | 10 | 64 | — | — | — | — | — |
| C (URAM-lean) | High pixel rate | 12 | 64 | ↓ | ↑ | — | — | — |
NEXT STEP
Want to see it in your pipeline?
Share your formats, resolutions, and target device. We’ll map a configuration (taps/phases/memory strategy) and provide integration package details.
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Integration-ready interfaces
AXI4-Stream + AXI4-Lite -
Low-latency streaming
Built for real-time systems
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Quality knobs that matter
Taps, phases, coefficients -
Portability
Structured RTL for porting