RISC-V Summit Europe

We propose an end-to-end open-source design for a low-cost, modular BFloat16 FPU microarchitecture for RISC-V embedded cores. Our design relaxes certain features of the IEEE Floating-Point Standard to realize a cost-effective hardware implementation that is integrated with cv32e40p (RI5CY core).

Using these optimizations, we have achieved almost 35% reduction in silicon area compared to an IEEE compliant FP32 implementation with minimal impact on accuracy.

Come visit us at poster stand B-13 on Thursday, June 27th at RISC-V EU Summit, Germany to learn more!

#RISCV #RISCVSummitEurope #AI #MachineLearning #BFloat16