RISC-V: Tomorrows Processing Power

RISC-V is an open standard instruction set architecture (ISA) that is being readily adopted to transform processors from data centers to AI-on-the-edge. 10xEngineers is a development partner of RISC-V International and a contributor to the ratification of RISC-V ISA. Our team of 70+ engineers collaborates with the leading RISC-V companies to accelerate their market to time.

Our Expertise

RISC-V Design Services

RISC-V has emerged as a promising, open-source alternative in the ever-evolving landscape of processor architectures. As the demand for computational power continues to surge, enhancing RISC-V core performance becomes imperative. At 10xEngineers, our dedicated RISC-V core and uncore IP Design team is continuously exploring ways to push the boundaries of RISC-V capabilities. A key focus of our open-source efforts is the OpenHW Group’s CVA6 core, an application-class RISC-V processor. Simultaneously, we leverage our deep expertise in processor design and verification to partner with customers, accelerating their time-to-market while ensuring superior design and performance quality.

RISC-V Verification Services

Tap into our RISC-V verification solution to build modern and complex systems within remarkably short timeframes. Our expert verification team specializes in:

Core Verification

Our team has extensive expertise in verifying RISC-V in-order and out-of-order cores. We have experience working with both privileged and unprivileged specifications and vector extensions of RISC-V.

IP Verification

We assist our customers in verifying various IP, including I3C, JTAG, AIA, IOMMU, and Die-to-Die (Chiplets) interfaces. Our verification process utilizes either third-party VIPs (Cadence, Avery) or internally developed VIPs to ensure thorough and accurate validation.

Deep Learning Accelerator Verification

Our team has developed and integrated the UVM verification environment with existing UVCs to enable comprehensive full-chip design verification for a neural accelerator, creating detailed test plans and coverage plans.

Development of UVM Testbenches

We developed and enhanced UVM testbenches for multiple RISC-V extensions and IPs, ensuring thorough coverage of key features by developing and implementing test plans.

Test Generators

We help you to integrate industry-standard random and automated test generators, including STiNG (Valtrix), RISCV-DV, Torture, and Imperas, into testbenches for enhanced verification coverage.

Code Coverage and Regression Management

We ensure comprehensive code and functional coverage closure by using directed and random tests, along with guided UNR. Our approach also includes regression triage and CI testing to uphold the highest standards of quality.

RISC-V Software Development Services

For the fast growing RISC-V ecosystem, software is a key element that can determine success. 10xEngineers offers some key software development services that can help reduce the Time to Market for your product.

Clients Testimonials

Florian 'Flo' Wohlrab

Head of OpenHW Foundation

“10xEngineers have made outstanding contributions to the OpenHW community since joining in 2021, playing a key role in advancing the functionality, verification, and compliance of CVA6 and also CV-Wally. Their work spans across architectural and microarchitectural verification, adding key RISC-V extensions—including bit manipulation, Zce, Zicond, and scalar cryptography—and significantly improving verification infrastructure like core-v-verif and cvw-arch-verif. Their efforts to support RVV 1.0 in Force Simulator via the ARA implementation, including vector instruction implementation and test generation, reflect both deep technical expertise and a strong commitment to open-source innovation. We greatly value their ongoing contributions and counting on 10xEngineers for advancing OpenHW Foundation industrial quality, open Source RISC-V Cores.”

Woodpecker Technologies

“Woodpecker Technologies engaged with 10xEngineers to develop an LLVM-based tool that enhances the post-silicon validation process by leveraging two decades of Stanford research on Quick Error Detection (QED) algorithms. This tool has significantly reduced Error Detection Latency (EDL) and improved the error coverage of our post-silicon tests. The 10xEngineers team provided exceptional compiler expertise throughout the project. We are extremely pleased with the expertise, professionalism, and dedication demonstrated by 10xEngineers. We look forward to collaborating with them on future initiatives.”

Prof. David Harris

Harvey Mudd College

During the 2024-25 academic year, 10xEngineers has sponsored a Global Clinic Project to develop open-source architectural functional coverage for RISC-V microprocessors. The project has involved students and faculty at Harvey Mudd College in California and UET and Habib University in Pakistan. 10xEngineers liaisons have mentored the students and trailblazed several of the critical technical components. The project has produced open-source testplans, SystemVerilog coverpoints, and tests for both RV32 and RV64 through the RVA22S64 profile, for unprivileged instructions as well as privileged features including CSRs, exceptions, interrupts, virtual memory, and endianness https://github.com/openhwgroup/cvw-arch-verif. The 10xEngineers liaisons specifically have contributed the testplans and coverpoints for virtual memory, which is the most complex portion of the functional coverage, as well as guiding students through extending riscv-arch-test to hit these coverpoints. They have also integrated the riscvISACOV framework to collect coverage from a device under tests via the RISC-V Verification Interface (RVVI), guided students writing subtle SystemVerilog coverpoints, and met weekly to advise the student teams. We expect the students will be able to finish the remaining SV48, PMP, and interrupt coverpoints in the next month. This work will bring the OpenHW Foundation CORE-V Wally processor https://github.com/openhwgroup/cvw to Technology Readiness Level 5 and will greatly ease getting other RVA22S64 and simpler cores to a similar level of verification. It is also being considered by the RISC-V Certification Steering Committee as a basis for open-source certification. The team has submitted a paper to the 2025 RISC-V summit describing their work. Overall, it has been a delight collaborating with 10xEngineers. Their deep technical knowledge, hard work, and long-standing commitment to the RISC-V open-source ecosystem have made this project possible.

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