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Agentic kernel & graph optimization

Prove every optimization on real hardware.

KernelX proposes, runs, verifies and improves kernel and graph optimizations on your accelerator.

One optimization cycle
PROPOSE
RUN
VERIFY
IMPROVE
Loops continuously
What is KernelX

An agentic loop for kernels and compute graphs

KernelX is an agentic optimization tool for accelerator kernels and compute graphs.

It proposes an optimization, runs it on real hardware, verifies correctness, and keeps improving it. An end-to-end, evidence-driven loop.

  • Propose. Selects an optimization for a kernel or graph pass.
  • Run. Executes it on real hardware.
  • Verify. Checks correctness before it counts.
  • Improve. Keeps what's faster and loops.

Bring your chip's capability model to life.

Tell us about your accelerator.

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How it works

How KernelX optimizes performance

KernelX doesn't optimize the hardware. It optimizes performance on the hardware, by learning what the chip is capable of and testing proven techniques against that capability on real silicon.

It builds a capability model and runs a loop that:

01

Analyze capability

Models what the chip can do.

02

Select optimizations

Chooses kernel-level techniques to test.

03

Run graph passes

Fusion, parallelization, scheduling.

04

Embed & verify

Verifies performance end-to-end in a runtime like llama.cpp.

05

Record & catalogue

Logs what works for the next pass.

Loops back into 01
For hardware teams

What a hardware team gets

Enablement

Full model enablement

A complete model running end-to-end, verified in a real runtime.

Automation

Automated optimization

Graph and kernel optimization run as a loop, not a manual pass.

Velocity

Faster time to develop

Development and iteration with minimal human intervention.

Knowledge

Capability model & catalogue

Reusable knowledge of what works on the chip.

Signal

Feedback on the silicon

Evidence that informs the next hardware revision.

Case study

Deploying ML models on custom hardware, with continuous improvement

Fewer abstractions, open platforms, and LLMs working under expert guidance make continuous improvement on new silicon fast, explainable and repeatable.

The problem

New hardware needs a scalable AI compiler, fast.

  • Costly and complicated. Stacks with many IRs that don't scale with changing AI workloads.
  • Slow development. Long bring-up latency and a long tail of performance work.
  • Lack of experts. Few people can reason across workload, compiler and hardware at once.
What needs to change
  • 01Collapse unnecessary abstractions across the stack.
  • 02Few experts, many agents, for quick enablement.
  • 03Increase performance through KernelX — self-improving kernel generation with expert oversight, built on open-source platforms.
In production

A performant MoE model on a 1,000+ core system, in days, through llama.cpp

AiNekko ET-SOC-1
A 1,000+ core RISC-V accelerator
~150 TOPS · non-coherent NoC · multi-hierarchy memory · scalar, vector and asynchronous tensor units
Qwen 3.5 35B A3B (MoE), single user, 4-bit quantized — decode tokens/sec
Day 12.4 tok/s Day 514.6 tok/s
Beats expert-only performance

Automatic self-improvement with expert oversight, under a limited token budget.

LPDDR4 DRAM, Minion cores at 600MHz. Esperanto Technologies' internal stack reached 11.51 tok/s on a Llama 3 8B model for comparison.

2x / 4x

2x the raw decode throughput on a 4x bigger model, versus the native stack. No in-house algorithmic tricks or runtime customization, just better hardware utilization, workload understanding and KernelX. Repeatable for your hardware.

Let's talk about your hardware

Tell us about your accelerator and where performance is falling short.

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